A plan view of a prior-art R-2R resistance ladder 500 as disclosed in Japanese Patent Publication No. 2-28269 is shown in FIG. 19, and an equivalent circuit diagram of the resistance ladder 500 of FIG. 19 is shown in FIG. 20.
This resistance ladder 500 comprises adjacent resistance groups 501 and 502. Each of the resistance groups 501 and 502 is provided with first to third resistors 511, 512, and 513. As shown in FIG. 20, the first resistor 511 is a resistor that forms one resistance (R) of the R-2R resistance ladder 500 and the second and third resistors 512 and 513 are resistors that form a combined resistance (2R). In FIG. 19, the first and third resistors 511 and 513 are disposed on either side of the second resistor 512.
An insulation layer (not shown in the figure) is formed above these first to third resistors 511 to 513. A wiring layer 515, indicated by hatching in FIG. 19, is formed above the insulation layer. The wiring layer 515 is connected to the first to third resistors 511 to 513 via contact holes 520. Note that a driver circuit is connected to the third resistor 513.
However, with this structure, the surface areas of the wiring layer 515 corresponding to each of the first to third resistors 511 to 513 are different. In particular, the surface area of the wiring layer 515 corresponding to the third resistor 513 is extremely small. Thus the presence of the wiring layer 515 corresponding to regions above the first to third resistors 511 to 513 causes the resistances of the first to third resistors 511 to 513 to vary due to piezoelectric effects, and moreover the amounts of these variations are different in each of the first to third resistors 511 to 513.
If a digital-to-analog converter (hereinafter called a D/A converter) is configured by using this resistance ladder, therefore, the conversion accuracy thereof will be inferior.
In another resistance ladder of the prior art, the driver circuits connected to the third resistors 513 of adjacent resistance groups 501 and 502 are not disposed at one side in the direction indicated by X in FIG. 19, but are disposed separately at one end and the other end thereof in the X direction. In this case, it is not possible to gather together the driver circuits at one side portion of the resistance ladder, so that an increased region of the layout of the semiconductor device is wasted, which leads to an increase in the chip surface area.
An objective of this invention is to provide a resistance ladder in which the amounts of variation in resistance caused by the correspondence between the resistors and the wiring layer are substantially the same for all resistors, and which enables a reduction in the surface area of the layout, together with a digital-to-analog converter and a semiconductor device that use this resistance ladder.
Another objective of this invention is to provide a resistance ladder which makes it possible to dispose a plurality of driver circuits at one side of a resistor formation region, together with a digital-to-analog converter and a semiconductor device that use this resistance ladder.